View STV0056AF_415866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STV0056AF
SATELLITE SOUND AND VIDEO PROCESSOR
VIDEO COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN CONTROL COMPOSITE VIDEO SELECTABLE INVERTER TWO SELECTABLE VIDEO DE-EMPHASIS NETWORKS 6 x 3 VIDEO MATRIX BLACK LEVEL ADJUSTABLE OUTPUT FOR ON-BOARD VIDEOCRYPT DECODER HIGH IMPEDANCE MODE VIDEO OUTPUTS FOR TWIN TUNER APPLICATIONS MISCELLANEOUS 22kHz TONE GENERATIONFOR LNB CONTROL I2C BUS CONTROL CHIP ADDRESSES = 06HEX OR 46HEX LOW POWER STAND-BY MODE WITH ACTIVE AUDIO AND VIDEO MATRIXES
. . . . . . . . . . . . . . . . .
SOUND TWO INDEPENDENT SOUND DEMODULATORS PLL DEMODULATION WITH 5-10MHz FREQUENCY SYNTHESIS PROGRAMMABLE FM DEMODULATOR BANDWIDTH ACCOMODATING FM DEVIATIONS FROM 30kHz TILL 400kHz PROGRAMMABLE 50/75s, J17 OR NO DEEMPHASIS WEGENER PANDA SYSTEM TWOAUXILIARYAUDIO INPUTS ANDOUTPUTS GAIN CONTROLLED AND MUTEABLE AUDIO OUTPUTS HIGH IMPEDANCE MODE AUDIO OUTPUTS FOR TWIN TUNER APPLICATIONS
TQFP64 (10 x 10mm) (Thin Plastic Quad Flat Pack) ORDER CODE : STV0056AF
DESCRIPTION The STV0056AF BICMOS integratedcircuit realizes all the necessary signal processing from the tuner to theAudio/Videoinput andoutputconnectors regardless the satellite system.
February 1998 1/27
STV0056AF
PIN CONNECTIONS
VIDEEM2/22kHz UNCL DEEM S2 VID OUT S2 VID RTN B-BAND IN
CLAMP IN
S2 OUT R
S2 OUT L
VIDEEM1
VGND
VGND
VOL L
V 12V
V 12V
16 15 14 13 12 11 10 9
S2 RTN L S2 RTN R FM IN S3 RTN L S3 RTN R AGC L S3 OUT L S3 OUT R IO SCL SDA HA J17 R J17 L XTL VDD 5V
8
7
6
5
4
3
2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
GND
NC
1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
S1 VID OUT S3 VID OUT VOL R S3 VID RTN S1 VID RTN LEVEL R PK IN R FC R AGND R FC L PK IN L LEVEL L PKOUT L PKOUT R IREF CPUMP R
PIN ASSIGNMENT
Pin Number 1 2 3 4 5 6 7 8 9 10 - 11 12 13 - 14 15 16 17 18 19 20 Name GND S2 VID OUT VOL L S2 VID RTN S2 OUT L CLAMP IN S2 OUT R UNCL DEEM VIDEEM2/22kHz V 12V VIDEEM1 V GND NC B-BAND IN S2 RTN L S2 RTN R FM IN S3 RTN L Base Band Input Auxiliary Audio Return Left (from VCR) FM Demodulator Input Auxiliary Audio Return Left (from decoder)
0056F-01.TBL
Function Connected to the Lead Frame VCR-Scart 2 Video Output Volume Controlled Audio Out Left VCR-Scart 2 Video Return Fixed Level Audio Output Left (to VCR) Sync-Tip Clamp Input Fixed Level Audio Output Right (to VCR) Unclamped Deemphasized Video Output Video Deemphasis 2 or 22kHz Output Video 12V Supply Video Deemphasis 1 Video Ground
Auxiliary Audio Return Right (from VCR)
2/27
0056F-01.EPS
NC
NC
AGND L
AGND L
DET L
U75 L
AMPLK R
DET R
AGC R
GND 5V
CPUMP L
AMPLK L
U75 R
A 12V
A 12V
VREF
STV0056AF
PIN ASSIGNMENT (continued)
Pin Number 21 22 23 24 25 26 27 28 29 30 31 32 34 33 35 36 37 38 39 40 41 - 42 43 44 - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name S3 RTN R AGC L S3 OUT L S3 OUT R I/O/22kHz SCL SDA HA J17 R J17 L XTL VDD 5V NC GND 5V CPUMP L DET L U75 L AMPLK L AGC R NC A GND L VREF A 12V AMPLK R DET R U75 R CPUMP R IREF PK OUT R PK OUT L LEVEL L PK IN L FC L A GND R FC R PK IN R LEVEL R S1 VID RTN S3 VID RTN VOL R S3 VID OUT S1 VID OUT Audio Ground 2.4V Reference Audio 12V Supply Amplitude Detector Capacitor Left FM PLL Filter Right Deemphasis Time Constant Right FM PLL Charge Pump Capacitor Right Current Reference Resistor Noise Reduction Peak Detector Output Right Noise Reduction Peak Detector Output Left Noise Reduction Level Left Noise Reduction Peak Detector Input Audio Roll-off Left Audio Ground Audio Roll-off Right Noise Reduction Peak Detector Input Right Noise Reduction Level Right TV-Scart 1 Video Return Decoder-Scart Video Return Decoder-Scart Video Output TV-Scart 1 Video Output
0056F-01.TBL
Function Auxiliary Audio Return Right (from decoder) AGC Peak Detector Capacitor Left Auxiliary Audio Output L (to decoder) Auxiliary Audio Output R (to decoder) Digital Input/Output or 22kHz Output I2C Bus Clock I2C Bus Data Hardware Address J17 Deemphasis Time Constant Right J17 Deemphasis Time Constant Left 4/8MHz Quartz Crystal or Clock Input Digital 5V Power Supply Not Connected Digital Power Ground FM PLL Charge Pump Capacitor Left FM PLL Filter Left Deemphasis Time Constant Left Amplitude Detector Capacitor Left AGC Peak Detector Capacitor Right
Volume Controlled Audio Out Right
3/27
STV0056AF
PIN DESCRIPTION 1 - Sound Detection
FMIN This is the input to the two FM demodulators. It feeds two AGC amplifiers with a bandwidth of at least 5-10MHz. There is one amplifier for each channel both with the same input. The AGC amplifiers have a 0dB to +40dB range. ZIN = 5k, Min input = 2mVPP per subcarrier. Max input = 500mVPP (max when all inputs are added together, when their phases coincide). AGC L, AGC R AGC amplifiers peak detector capacitor connections. The output current has an attack/decayratio of 1:32. That is the ramp up current is approximately 5A and decay current is approximately 160A. 11V gives maximum gain. These pins are also driven by a circuit monitoring the voltage on AMPLK L and AMPLK R respectively. AMPLK L, AMPLK R The outputs of amplitude detectors LEFT and RIGHT. Each requires a capacitor and a resistor to GND. The voltage across this is used to decide whether there is a signal being received by the FM detector. The level detector output drives a bit in the detector I2C bus control block. AMPLK L and AMPLK R drive also respectively AGC L and AGC R. For instance when the voltage on AMPLK L is > (VREF + 1 VBE) it sinks current to VREF from pin AGCL to reduce the AGC gain. DET L, DET R Respectively the outputs of the FM phase detector left and right. This is for the connection of an external loop filter for the PLL. The output is a push-pull current source. CPUMP L, CPUMP R The output from the frequency synthesizer is a push-pullcurrent sourcewhich requiresa capacitor
to ground to derive a voltage to pull the VCO to the target frequency. The output is 100A to achieve lock and 2A during lock to provide a tracking time constant of approximately 10Hz.
VREF This is the audio processor voltage reference used through out the FM/audio section of the chip. As such it is essential that it is well decoupled to ground to reduce as far as possible the risk of crosstalk and noise injection. This voltage is derived directly from the bandgap reference of 2.4V. The VREF output can sink up to 500A in normal operation and 100A when in stand-by. IREF This is a bufferedVREF outputto an off-chipresistor to produce an accurate current reference, within the chip, for the biasing of amplifiers with current outputs into filters. It is also required for the Noise reduction circuit to provide accurate roll-off frequencies. This pin should not be decoupled as it would inject current noise. The target current is 50A 2% thus a 47.5k 1% is required. A 12V Double bonded main power pin for the audio/FM section of the chip. The two bond connections are to the ESD and to power the circuit and on chip regulators/references. A GND L This ground pin is double bonded : 1) to channel LEFT : RF section & VCO, 2) to both AGC amplifiers, channel LEFT and RIGHT audio filter section. A GND R This ground pin is double bonded : 1) to the volume control, noise reduction system, ESD + Mux + VREF 2) to channel right : RF section & VCO
4/27
STV0056AF
PIN DESCRIPTION (continued) 2 - Baseband Audio Processing
PK OUT L, PK OUT R, PK OUT The noise reduction control loop peak detector output requires a capacitor to ground from this pin, and a resistor to VREF pin to give some accurate decaytime constant.An on chip5k 25 % resistor and external capacitor give the attack time. PK IN L, PK IN R or PK IN Each of thesepins is an input to a control loop peak detector and is connected to the output of the offchip control loop band pass filter. LEVEL L, LEVEL R Respectively the audio left and right signals of the FM demodulators are output to level L and level R pins through an input follower buffer. The off-chip filters driven by these pins must include AC coupling to the next stage (PK IN L and PK IN R pins respectively). FC L, FC R The variable bandwidth transconductance amplifier has a current output which is variable depending on the input signal amplitude as defined by the control loop of the noise reduction. The output current is then dumped into an off-chip capacitor which together with the accurate current reference define the min/max rolloff frequencies.A resistor in series with a capacitor is connectedto ground from these two pins. J17 L, J17 R The external J17 de-emphasis networks for channels left and right. The amplifier for this filter is voltage input, current output. Output with 500mV input will be 55A. To perform J17 de-emphasiswith the STV0042,an external circuit is required.
U75 L, U75 R External deemphasis networks for channels left and right. For each channela capacitorand resistor in parallel of 75s time constant are connected between here and VREF to provide 75s de-emphasis. Internally selectable is an internal resistor that can be programmedto be added in parallel thereby converting the network to approx 50s de-emphasis (see control block map). The value of the internal resistors is 54k 30 %. The amplifier for this filter is voltage input, current output ; with 500mV input the output will be 55A. VOL L, VOL R The main audio output from the volume control amplifier the signal to get output signals as high as 2VRMS (+12dB) on a DC bias of 4.8V. Control is from +12dB to -26.75dB plus Mute with 1.25dB steps. This amplifier has shortcircuitprotectionand is intendedto drive a SCART connectordirectly via AC coupling and meets the standard SCART drive requirements. These outputs feature high impedance mode for parallel connection. S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R These audio outputs are sourced directly from the audio MUX, and as a result do not include any volume control function. They will output a 1VRMS signal biased at 4.8V. They are short circuit protected. These outputs feature high impedance mode for parallel connection and meet SCART drive requirement. S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R These pins allow auxiliary audio signals to be connected to the audio processor and hence makes use of the on-chip volume control. For additional details please refer to the audio switching table.
5/27
STV0056AF
PIN DESCRIPTION (continued) 3 - Video Processing
B-BAND IN AC-coupled video input from a tuner. ZIN > 10k 25%. This drives an on-chip video amplifier. The other input of this amp is AC grounded by being connected to an internal VREF. The video amplifier has selectable gain from 0dB to 12.7dB in 63 steps and its output signal can be selected normal or inverted. UNCL DEEM Deemphasized still unclamped output. It is also an input of the video matrix. VIDEEM1 Connected to an external de-emphasis network (for instance 625 lines PAL de-emphasis). VIDEEM2 / 22kHz Connected to an external de-emphasis network (for instance 525 lines NTSC or other video de-emphasis).Alternatively a precise 22kHz tone may be output by I2C bus control. CLAMP IN This pin clamps the most negative extreme of the input (the sync tips) to 2.7VDC (or appropriate voltage). The video at the clamp input is only 1VPP. This clamped video which is de-emphasised, filtered and clamped (energy dispersal removed) is normal, negative syncs, video. This signal drives the Video Matrix input called Normal Video. It has a weak (1.0A 15 %) stable current source pulling the input towards GND. Otherwise the input impedance is very high at DC to 1kHz ZIN > 2M. Video bandwidth through this is -1dB at 5.5MHz. The CLAMP input DC restore voltage is then used as a means for getting the correct DC voltage on the SCART outputs. S3 VID RTN This input can be driven for instance by the decoder. This input has a DC restoration clamp on its input. The clamp sink current is 1A 15% with the buffer ZIN > 1M. S2 VID RTN, S1 VID RTN External video input 1.0Vpp AC coupled75 source impedance. This input has a DC restoration clamp on its input. The clamp sink current is 1A 15% with the buffer ZIN > 1M. This signal is an input to the Video Matrix. S1 VID OUT, S2 VID OUT Video drivers for SCART 1 and SCART 2. An external emitter follower buffer is required to drive a 150 load. The average DC voltage to be 1.5V
6/27
on the O/P. The signal is video 2.0VPP 5.5MHz BW with sync tip = 1.2V. These pins get signals from the Video Matrix. The signal selected from the Video Matrix for output on this pin is controlled by a control register. This output also feature a high impedance mode for parallel connection.
S3 VID OUT This output can drive for instance a decoder. Also it is able to pass 10MHz ; ZOUT < 75. Video on this pin will be 2VPP. The black level of the ouput video signal can be adjusted through I2C bus control to easily interface with on-board Videocrypt decoder. This output feature an high impedance mode for parallel connection. V 12V + 12V double bonded : ESD+guard rings and video circuit power. V GND Doubled bonded. Clean VID IN GND. Strategically placed video power ground connection to reduce video currents getting into the rest of the circuit.
4 - Control Block
GND 5V The main power ground connection for the control logic, registers, the I2C bus interface, synthesizer & watchdog and XTLOSC. VDD 5V Digital +5V power supply. SCL This is the I2C busclock line. Clock = DC to 100kHz. Requires external pull up eg. 10k to 5V. SDA This is the I2C bus data line. Requires external pull up eg. 10k to 5V. I/O / 22kHz General purpose input output pin or 22kHz output. XTL This pin allows for the on-chip oscillator to be either used with a crystal to ground of 4MHz or 8MHz, or to be driven by an external clock source. The external source can be either 4MHz or 8MHz. A programmablebit in the control block removes a /2 block when the 4MHz option is selected. HA Hardware address with internal 135A pull down. Chip address is 06 when this pin is grouded and chip address is 46 when connected to VDD.
STV0056AF
GENERAL BLOCK DIAGRAM
From Tuner
B-BAND 2 Video Processing 4
6x3 Video Matrix
3
From TV, VCR/Decoder From Tuner
2 FM Demodulation 2 Channels Wegener Panda + Deemphasis To TV, VCR/Decoder Audio Matrix + Volume
3
STV0056AF
VIDEO PROCESSING BLOCK DIAGRAM
LPF NTSC PAL VIDEEM2/22kHz
9
Active in Stand-by
VIDEEM1
12 8
UNCL DEEM
I/O/22kHz 25 22kHz TONE /2 B-BAND IN 16 G 1 Baseband CLAMP IN
6
Deemphasized
CLAMP
Normal
S3 VID RTN
61
CLAMP
Decoder Return
S2 VID RTN
4
CLAMP
VCR Return
S1 VID RTN
60
CLAMP
TV Return BLACK LEVEL ADJUST
STV0056AF
63 S3 VID OUT To Decoder
64
2
S1 VID OUT
S2 VID OUT To VCR To TV
0056F-03.EPS
7/27
0056F-02.EPS
22kHz to LNB
I2C Bus Interface
STV0056AF
AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL RIGHT)
STV0056AF
a K2 b a b K3 4 abc K5 6dB -6dB 47 DET R 24 S3 OUT R 21 S3 RTN R 51 58 59 57 PK OUT R FC R LEVEL R PK IN R 29 J17 R 48 U75 R 7 S2 OUT R -6dB 18 S2 RTN R 62 VOL R c AUDIO DEEMPHASIS
a b c
K1
AUDIO R abc K6 6dB K4 b
ANRS
MONO STEREO
a
PLL FILTER
Audio Decoder Out DECODER
Audio Decoder Return VCR TV
0056F-04.EPS 0056F-05.EPS
AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL LEFT)
STV0056AF
a K2 b a b K3 4 abc K5 6dB -6dB 36 DET L 23 S3 OUT L 20 S3 RTN L 52 54 53 55 PK OUT L PK IN L LEVEL L FC L 30 J17 L 37 U75 L 5 S2 OUT L c AUDIO DEEMPHASIS
a b c
K1
AUDIO L K4 b
ANRS
MONO STEREO
abc K6 6dB
a
-6dB 17 S2 RTN L VOL L TV 3
PLL FILTER Audio Decoder Out
Audio Decoder Return DECODER VCR
8/27
STV0056AF
AUDIO SWITCHING
AUDIO DEEMPHASIS + ANRS AUDIO PLL K 1a K5b K6c
K4 : a ANRS input non-scrambled audio b ANRS input descrambled audio
K2 a b1 b2 c a b1 b2 c K3 a a a a b b b b No ANRS, No De-emphasis No ANRS, 50s No ANRS, 75s No ANRS, J17 ANRS, No De-emphasis ANRS, 50s ANRS, 75s ANRS, J17
K5c
K6a
DEC RTN
K 1b
K5a
VOL OUT AUX OUT
DEC OUT
FM DEMODULATION BLOCK DIAGRAM
0056F-06.EPS
AUX IN
K 1c
K6b
FM IN 19
SW1 AGC LEVEL DETECTOR 1
Phase Detect FM dev. Select.
47 DET R
AUDIO R
Bias
AGC R 39
49 CPUMP R
LEVEL DETECTOR 2 Amp. Detect
AMPLK R 46
VREF
90 VCO 0 WATCHDOG VREF Reg8 b4 SYNTHESIZER SW4 AUDIO L SW3 AGC LEVEL DETECTOR 1 Phase Detect FM dev. Select.
35 CPUMP L 36 DET L
SW2
Bias
AGC L 22
LEVEL DETECTOR 2 Amp. Detect
AMPLK L 38
VREF
90 VCO 0 WATCHDOG VREF Reg8 b0
0056F-07.EPS
STV0056AF
9/27
STV0056AF
CIRCUIT DESCRIPTION Video Section The composite video is first set to a standard level by means of a 64 step gain controlled amplifier. In the casethat themodulationis negative,an inverter can be switched in. One of two different external video de-emphasis networks (for instance PAL and NTSC) is selectable by an integrated bus controlled switch. Then energy dispersal is removed by a sync tip clamping circuit, which is used on all inputs to a video switching matrix, thus making sure that no DC steps occur when switching video sources. The matrix can be used to feed video to and from decoders, VCR's and TV's. A bus controlled black level adjustment circuit is provided on the decoder output allowing a direct connection to an on-board Videocrypt decoder. Additionaly all the video outputs are tristate type (high impedance mode is supported), allowing a simple parallel connections to the scarts (Twin tuner applications). Audio Section The two audio channels are totally independent except for the possibility given to output on both channelsonly one of the selectedinput audio channels. To allow a very cost effective application, each channel uses PLL demodulation. Neither external complex filter nor ceramic filters are needed. The frequency of the demodulated subcarrier is chosen by a frequency synthesizer which sets the frequency of the internal local oscillator by comparing its phase with the internally generated reference. When the frequency is reached, the microprocessor switches in the PLL and the demodulationstarts. Atany moment the microprocessor can read from the device (watchdog registers) the actual frequency to which the PLL is locked. It canalso verify that a carrier is present at the wanted frequency(by reading AMPLK status bit) thanks to a synchronous amplitude detector, which is also used for the audio input AGC. In order to maintain constant amplitude of the recovered audio regardless of variations between satellites or subcarriers, the PLL loop gain may be programmed from 56 values. Any frequency deviation can be accomodated (from 30kHz till 400kHz). Two different networks can be permanently connected for either 75s or J17 de-emphasis. If 50s de-emphasisis required,this can be inserted by an internal switch, thus allowing a worldwide application. The STV0056AF is intended to be compatible with Wegener Panda System. Two types of audio outputs are provided : one is a fixed 1VRMS and the other is a gain controlled 2VRMS max. The control range being from +12dB to -26.75dBwith 1.25dB steps. This output canalso be muted. A matrix is implemented to feed audio to and from decoders VCR's and TV's. Noise reduction system and de-emphasis can be inserted or by-passed through bus control. Also all the audio outputs are tristate-type (high impedance mode is supported), allowing a simple parallel connections to the scarts (Twin tuner applications). Others A 22kHz tone is generated for LNB control. It is selectable by bus control and available on one of the two pins connected to the external video de-emphasis networks. One general purpose I/O is also available on the STV0056AF. By means of the I2C bus there is the possibility to drive the ICs into a low power consumption mode with active audio and video matrixes. Independantly from the main power mode, each individual audio and video output can be driven to high impedance mode.
10/27
STV0056AF
ABSOLUTE MAXIMUM RATINGS
Symbol V CC V DD Ptot Toper Tstg Supply Voltage Total Power Dissipation Operating Ambient Temperature Storage Temperature Parameter Value 15 7.0 900 0, + 70 -55, + 150 Unit V V
o o
C C
Symbol Rth(j-a)
Parameter Thermal Resistance Junction-ambient Max.
Value 55
Unit
o
C/W
DC AND AC ELECTRICAL CHARACTERISTICS (VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified)
Symbol VCC VDD IQ CC IQ DD IQLPCC IQLPDD FMIN Parameter Sypply Voltage Supply Current Supply Current at Low Power Mode All audio and all video outputs activated All audio and all video outputs are in high impedance mode VCO locked on carrier at 6MHz 560k load on AMPLOCK Pins 180k load on DET Pins 8mVPP FMIN 500mVPP Carrier without modulation VCC : 11.4 to 12.6V, Tamb : 0 to 70oC 0.5VPP 50kHz dev. FM input, Coarse deviation set to 50kHz (Reg. 05 = 36HEX) 0.5VPP 50kHz dev. FM input, Coarse and fine settings used Gain at 12kHz versus 1kHz 180k, 82k 22pF on DET Pins Average sink and source current to external capacitor 1VPP on left and right channel 5 Test Conditions Min. 11.4 4.75 Typ. 12 5.0 55 8 27 6 Max. 12.6 5.25 70 15 35 9 500 Unit V V mA mA mA mA mVPP V MHz MHz VPP VPP dB A
AUDIO DEMODULATOR FM Subcarrier Input Level (Pin FMIN for AGC action) Detector 1 and 2 (AMPLOCK Pins) (Threshold for activating Level Detector 2) VCO Mini Frequency VCO Maxi Frequency 1kHz Audio Level at PLL output (DET Pins) 1kHz Audio Level at PLL output (DET Pins) FM Demodulator Bandwidth Digital Phase Comparator Output Current (CPUMP Pins) Output Level (Pins LEVEL) Level Detector Output Resistance (Pins PK OUT) Level Detector Fall Time Constant (Pins PK OUT) Bias Level (Pins PK OUT) Noise Reduction Cut-off Frequency at Low Level Audio Noise Reduction Cut-off Frequency at High Level Audio
DETH VCOMI VCOMA AP50
2.90
3.10
3.30 5
10 0.6
1
1.35
APA50 FMBW DPCO
0.92 0
1 0.3 60
1.08 1
AUTOMATIC NOISE REDUCTION SYSTEM LRS LDOR NDFT NDLL LLCF HLCF 0.9 4.0 1 5.4 26.4 2.40 0.85 7 1.1 6.8 VPP k ms V kHz kHz
11/27
0056F-05.TBL
External 22nF to GND and 1.2M to VREF No audio in 100mVPP on DET Pins, External capacitor 330pF (FC Pins) 1VPP on DET Pins, External capacitor 330pF (FC Pins)
0056F-04.TBL
THERMAL DATA
0056F-03.TBL
mW
STV0056AF
DC AND AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified)
Symbol DCOL AOLN Parameter DC Output Level Audio Output Level with Reg 00 = 1A Audio Output Level with Reg 00 = 1A Audio Output Level with Reg 00 = 1A Audio Output Level with Reg 00 = 1A Audio Output Attenuation with Mute-on. Reg 00 = 00. Max Attenuation before Mute. Reg 00 = 01. Audio Gain. Reg 00 = 1F. Attenuation of each of the 31 steps THD with Reg 00 = 1A THD with Reg 00 = 1A THD with Reg 00 = 1A Test Conditions Min. Typ. 4.8 1.9 Max. Unit V VPP VPP VPP VPP dB dB 7 dB dB % % % dB dB AUDIO OUTPUT (Pins VOL OUT R, VOL OUT L) FM input as for APA50 No de-emphasis, No pre-emphasis No noise reduction FM input as for APA50 50s de-emphasis, 27k//2.7nF load No pre-emphasis, No noise reduction FM input as for APA50 75s de-emphasis, 27k//2.7nF load No pre-emphasis, No noise reduction FM input as for APA50 J17 de-emphasis, 36k 4.7k 8.2nF load No pre-emphasis, No noise reduction 1V PP - 1kHz from S2 RTN Pins 1kHz, from S2 RTN Pins 1kHz, from S2 RTN Pins 1kHz 5 1.5 2.34
AOL50
2.0
3.3
4.0
AOL75
2.0
3.3
4.0
AOL17
2.0
3.2
4.0
AMA1 MXAT MXAG ASTP THDA1 THDA2 THDFM
60
65 32.75 6 1.25 0.15 0.3 0.3
1V PP -1kHz from S2 RTN Pins 2V PP -1kHz from S2 RTN Pins FM input as for APA50 75s de-emphasis, ANRS ON ACS Audio Channel Separation 1V PP -1kHz on S2 RTN Pins ACSFM Audio Channel Separation at 1kHz - 0.5 VPP - 50kHz deviation FM input on one channel - 0.5VPP no deviation FM input on the other channel - Reg 05 = 36HEX - 75s de-emphasis, no ANRS SNFM Signal to Noise Ratio FM input as for APA50, 75s de-emphasis, no ANRS, Unweighted SNFMNR Signal to Noise Ratio FM input as for APA50 75s de-emphasis, ANRS ON, Unweighted Audio Output Impedance Low impedance mode ZOUT L ZOUT H High impedance mode AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L) DCOLAO DC output level AOLNS Audio Output Level on S2 and S3 AOL50S Audio Output Level on S2 and S3 Audio Output Level on S2 and S3 Audio Output Level on S2 and S3 S2 to S3 Audio Gain and S3 to S2 Audio Gain THD on S2, Input in S3 Aux. input pins open circuit FM input as for APA50 No de-emphasis, No pre-emphasis No noise reduction FM input as for APA50 50s de-emphasis, 27k//2.7nF load No pre-emphasis, No noise reduction FM input as for APA50 75s de-emphasis, 27k//2.7nF load No pre-emphasis, No noise reduction FM input as for APA50 J17 de-emphasis, 36k 4.7k 8.2nF load No pre-emphasis, No noise reduction 1kHz 2V PP - 1kHz from Aux input pins
1 1
60
74 60
56
dB
69
dB k V VPP VPP VPP VPP dB %
0056F-06.TBL
30
18 44 4.8 2
55
1.55
2.42
2.0
3.4
4.0
AOL75S
2.0
3.4
4.0
AOL17S
2.0
3.3
4.0
AGAO THDA02 12/27
-1
0 0.04
+1 0.2
STV0056AF
DC AND AC ELECTRICAL CHARACTERISTICS (continued) (VCC = 12V, VDD = 5V, Tamb = 25oC unless otherwise specified)
Symbol THDAOFM ZOUT L ZOUT H I/O VIL VIH VOL VOH LNBT LNBD RESET RTCCU RTCCD RTDDU RTDDD VIDC ZVI DEODC DEOMX DGV INVG VISOG DEBW DFG ITMOD End of Reset Threshold for VCC Start of Reset Threshold for VCC End of Reset Threshold for VDD Start of Reset Threshold for VDD VID IN VID IN Input Impedance DC Output Level (Pins VIDEEM) Max AC Level before Clipping (Pins VIDEEM) Gain error vs GV @ 100kHz Inverter Gain Video Input to SCART Outputs Gain Bandwidth for 1VPP input measured on Pins VIDEEM Differential Gain on Sync Pulses measured on Pins VIDEEM Intermodulation of FM subcarriers with chroma subcarrier Clamp Input Sink Current Clamp Input Source Current Output Level on any Output when 1VPP CVBS input is selected for any other output Output Buffer Gain (Pins S1 VID OUT, S2 VID OUT, S2 VID OUT) DC Output Level Video Output Impedance Sync Tip Level on Selected Outputs (Pins S1 VID OUT, S2 VID OUT) Sync Tip Level at S3 VID OUT with Black Level Adjust VDD = 5V, VCC going up VDD = 5V, VCC going down VCC = 12V, VDD going up VCC = 12V, VDD going down External load current < 1A 2.25 7 2.25 2 -0.5 -0.9 -1 10 1 -60 8.7 7.9 3.8 3.5 2.45 11 2.45 2.65 14 2.65 V V V V V k V VPP dB dB MHz % dB Low Level Input High Level Input Low Level Output High Level Output Tone Frequency Tone Signal Duty Cycle 0.8 2.4 Isink= 2mA Isource = 2mA No load connected on I/O 3.2 22.2 49 0.2 4.6 22.2 50 0.4 22.2 51 V V V V kHz % Parameter THD on S2 or S3 Audio Output Impedance Test Conditions FM input as for APA50 75s de-emphasis, no ANRS Low impedance mode High impedance mode Min. Typ. Max. 0.3 60 44 1 100 55 Unit % k AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L) (continued)
30
COMPOSITE SIGNAL PROCESSING
GV = 0dB, Reg 01 = 00 GV = 0 to 12.7dB, Reg 01 = 00 3F De-emphasis amplifier mounted in unity gain, Normal video selected @ - 3dB with GV = 0dB, Reg 01 = 00 GV = 0dB, 1VPP CVBS + 0.5VPP 25Hz sawtooth (input : VID IN) 7.02 and 7.2MHz sub-carriers, 12.2dB lower than chroma VIN = 3V VIN = 2V @ 5MHz
0 -1 0
0.5 -1.1 1
CLAMP STAGES (Pins CLAMP IN, S1, S2, S3 VID RTN) ISKC ISCC XTK 0.5 40 1 50 TBD 1.5 60 A A dB
VIDEO MATRIX
BFG DCOLVH ZOUT HV VCL
@ 100kHz High impedance mode High impedance mode 1VPP CVBS through 10nF on input Register 4 b6 b7 00 01 10 11
1.87
2 0 23 1.3
2.13 0.2 30 1.55 V k V
16 1.05
VCL S3
1.36 1.52 1.67 1.84
V V V V 13/27
0056F-07.TBL
STV0056AF
PIN INTERNAL CIRCUITRY
S1 VID RTN, S2 VID RTN, S3 VID RTN, CLAMP IN 50A source is active only when VIDIN < 2.7V. Figure 1
VDD 9V 50A
UNCL DEEM Same as above but with no black level adjustment and slightly different gain.
Figure 4
60 VCC 12V 4
VDD 5V GND 0V
0056F-08.EPS
GND 0V 16.7k
S3 VID OUT I black level is I2C programmablefrom source16A to sink 33A equivalent to an offset voltage of -150mV to + 300mV. The 60 collector resistor is for short cct. protection.
Figure 2
60 VCC 12V 4 63 S3 VID OUT 2.3mA VID MUX GND 0V 10k 25k VREF 2.4V
0056F-09.EPS
VIDEEM1 Ron of the transistor gate is 10k.
Figure 5
6/2 10/2
0056F-12.EPS
VIDEEM1 12
125A
VIDEEM2 / 22kHz Ron of the transistor gate is 10k.
Figure 6
6/2 10/2 VIDEEM2/22kHz 9 125A
16.7k
I Black Level
GND 0V
S1 VID OUT, S2 VID OUT Same as above but with no black level adjustment.
Figure 3
60 VCC 12V 4 Pins 64 - 2 S1 VID OUT S2 VID OUT 10k 20k VREF 2.4V
0056F-10.EPS
VDD 5V 100/2 22kHz
0056F-13.EPS
60/2
VID IN
Figure 7
VREF 2.4V 10k
2.3mA VID MUX GND 0V
6.5k 85A 0.5pF GND 0V
0056F-14.EPS
20k GND 0V
B-BANDIN 16
14/27
0056F-11.EPS
Pins 60 - 4 61 - 6 S1 VID RTN S2 VID RTN S3 VID RTN CLAMP IN
10k
2.3mA IN GND 0V 10k 25k
8 UNCL DEEM
1A
VREF 2.4V
STV0056AF
PIN INTERNAL CIRCUITRY (continued)
PK OUT R, PK OUT L
Figure 8
VDD 9V 3.4V Clamp Audio 1
0056F-15.EPS
S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R 4.8V bias voltage is the same as the bias level on the audio outputs.
Figure 12
4.8V
0056F-19.EPS 0056F-23.EPS 0056F-22.EPS 0056F-21.EPS 0056F-20.EPS
1 Peak Detector
5k
Pins 51 - 52 PK OUT R PK OUT L
Pins 17 - 18 - 20 - 21 S2 RTN L - S2 RTN R S3 RTN L - S3 RTN R
25k 50A
FC L, FC R Ivar is controlled by the peak det audio level max. 15A (1VPP audio). Figure 9
Pin 55 - 57 FC L - FC R VDD 9V
FM IN The otherinput for each channelis internallybiased in the same way via 10k to the 2.4V VREF.
Figure 13
2.4V 10k FM IN 19 50A 10k Left Channel
1 1 Ivar
0056F-16.EPS
50A Right Channel
VOL OUT R, VOL OUT L Audio output with volume and scart driver with +12dB of gain for up to 2VRMS. The opamp has a push-pull output stage. Figure 10
Audio 2.4V Bias 30k 30k GND 0V 15k
0056F-17.EPS
IREF The optimum value if IREF is 50A 2% so an external resistor of 47.5k 1% is required.
Figure 14
2.4V 1 50 IREF
Pins 62 - 3 VOL OUT R VOL OUT L
4.8V
I/O / 22kHz The input is TTL compatible. The output is tri-stateable. Figure 15
180/2 I/O/22kHz 205 25 ESD 100/2 10/2 IIC Reg 91/2
S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R Same as above but with gain fixed at +6dB.
Figure 11
Audio 2.4V Bias 20k Pins 5 - 7 - 23 - 24 S2 OUT L S2 OUT R S3 OUT L S3 OUT R 20k GND 0V
0056F-18.EPS
MUX 22kHz
SCL This is the input to a Schmitt input buffer made with a CMOS amplifier.
Figure 16
205 SCL 26 ESD 24/4
15/27
STV0056AF
PIN INTERNAL CIRCUITRY (continued)
SDA Input same as above. Output pull down only : relies on external resistor for pull-up. Figure 17
SDA 27 600/2 GND 0V ESD 205 24/4
0056F-24.EPS
CPUMP L, CPUMP R An offset on the PLL loop filter will cause an offset in the two 1A currents that will prevent the PLL from drifting-off frequency. Figure 21
100A Pins 35-49 CPUMP L CPUMP R Dig Synth
1A Loop Filter Tracking 1A
I2
0056F-25.EPS
Pins 30 - 29 37 - 48 J17 L - J17 R U75 L - U75 R
I1
DET L, DET R I2 - I1 = f (phase error).
Figure 22
I2
0056F-29.EPS
HA Input with CMOS levels.
Figure 19
205 HA 28 150A GND 0V
0056F-26.EPS
Pins 36 - 47 DET L - DET R I1
25/2
ESD
10/2
AMPLK L, AMPLK R, AGC L, AGC R I2 and I1 from the amplitude detecting mixer. Figure 23
To VCA Pin 38 Pin 46 AMPLK L AMPLK R I2 2 I1 5A Pin 22 Pin 39 AGC L AGC R
XTL
Figure 20
3 XTL 31 750A
460 2 2
460
3
10k
0056F-27.EPS
GND 0V
VREF 2.4V
16/27
0056F-30.EPS
500A
750A
5pF
160A
0056F-28.EPS
J17 L, J17 R, U75 L, U75 R I1 - I2 = 2 x audio / 18k. eg 1VPP audio : 55A. The are internal switches to match the audio level of the different standards. Figure 18
100A
VCO Input
STV0056AF
PIN INTERNAL CIRCUITRY (continued)
VREF The 400A source is off during stand-by mode.
Figure 24
Vbg 1.2V 4 10k 400A
0056F-31.EPS
VDD 5V, GND 5V Connected to XTL oscillator and the bulk of the CMOS logic and 5V ESD. A GND Doubled bonded : - One pad connected to the left VCO, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. - The second pad is connected to both AGC amps and the deemphasis amplifiers, frequency synthesis and FM deviation selection circuit for both channels. A 12V Doubled bonded : - One pad connected to the ESD and guard ring. - The second pad is connected to the main power for all of the audio parts.
43 VREF (2.4V)
10k
GND 0V
LEVEL L, LEVEL R
Figure 25
VREF 2.4V SW Audio 49k 49k 50k 100A 1
0056F-32.EPS
Pins 59 - 53 LEVEL R LEVEL L
PK IN L, PK IN R
Figure 26
VREF 2.4V 1
0056F-33.EPS
A GND R Boubled bonded : - One pad connected to the right VCO, dividers, mixers and guard ring. The guard connection is star connected directly to the pad. - The second pad is connected to the bias block, audio noise reduction, volume, mux and ESD. A third bond wire on this pin is connected directly to the die pad (substrate). Figure 27
Pins 10 - 11 V 12V Video Pads Pins 13 - 14 V GND VDD 5V 32 Vpp BIP 10vpl Vmm 205 Digital Pads DZPN1 DZPN1 DZPN1
+ BIP 12V -
Pins 58 - 54 PK IN R PK IN L
To Peak Det 67k 100A
V 12V Doubled bonded (two bond wires and two pads for one package pin) : - One pad is connected to all of the 12V ESD and video guard rings. - The second pad is connected to power up the video block. V GND Doubled bonded : - One pad is connectedto power-up all of the video mux and I/O. - The second pad is only as a low noise GND for the video input.
GND 5V 33 Pins 41 - 42 A GND L A 12V Audio Pads Substrate A GND R 56
17/27
0056F-34.EPS
STV0056AF
I2C PROTOCOL 1) WRITING to the chip S-Start Condition P-Stop Condition CHIP ADDR - 7 bits. Programmable 06H or 46H (STV0056AF only) with Pin HA. W-Write/Read bit is the 8th bit of the chip address. A-ACKNOWLEDGE after receiving 8 bits of data/adress. REG ADDR DATA REG ADDR/A/DATA/A Example : S 06 W A 00 A 55 A 01 A 8F A P Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are 'X' or don't care ie only the first 3 bits are used. 8 bits of data being written to the register. All 8 bits must be written to at the same time. can be repeated, the write process can continue untill terminated with a STOP condition. If the REG ADDR is higher than 07 then IIC PROTOCOL will still be met (ie an A generated).
2) READING from the chip When reading, there is an auto-incrementfeature. This means any read command always starts by reading Reg 8 and will continue to read the following registers in order after each acknowledge or until there is no acknowledge or a stop. This function is cyclic that is it will read the same set of registers without re-addressing the chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3 registers in a cyclic fashion or all 5 registers in a cyclic fashion. Note only the last 5 of the 11 registers can be read. Reg0 bit 7 = L Start / chip add / R / A / Reg 8 / A/ Reg 9 / A / Reg 0A / A / Reg 8 / A / Reg 9 / A / Reg 0A /... / P / Reg0 bit 7 = H Start / chip add / R / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / ... / P / CONTROL REGISTERS Reg 0 write only Bit (default 00HEX) 0 L Select 5 bits audio volume control 00H = MUTE 1 L Select 5 bits audio volume control 01H = -26.75dB 2 L Select 5 bits audio volume control : : : : : 3 L Select 5 bits audio volume control 1.25dB steps up to 4 L Select 5 bits audio volume control 1FH = +12dB 5 L Audio mux switch K4 - ANRS I/P select (L = PLL) 6 L Audio mux switch K3 - ANRS select (L = no ANRS, H = ANRS) 7 L L = read 3 registers, H = read 5 registers Reg 1 write only Bit (default 00HEX) 0 L Select video gain bits 1 L Select video gain bits 00H = 0dB 2 L Select video gain bits 01H = +0.202dB 3 L Select video gain bits 02H = +0.404dB 4 L Select video gain bits n = + 0.202 dB * n 5 L Select video gain bits 3FH = + 12.73 dB 6 L Selected video invert (H = inverted, L = non inverted) 7 L Video deemphasis 1 / Video deemphasis 2 (L : VID De-em 1)
18/27
STV0056AF
CONTROL REGISTERS (continued) Reg 2 write only Bit (default F7HEX) 0 H Select video source for scart 1 O/P 1 H Select video source for scart 1 O/P 2 H Select video source for scart 1 O/P 3 L Select 4.000MHz or 8.000MHz clock speed (L = 8MHz) 4 H Select audio source for volume output (Switch K1) 5 H Select audio source for volume output (Switch K1) 6 H Select Left/Right/Stereo for volume output 7 H Select Left/Right/Stereo for volume output Reg 3 write only Bit (default F7HEX) 0 H Select video source for scart 2 O/P 1 H Select video source for scart 2 O/P 2 H Select video source for scart 2 O/P 3 L Video deemphais 2 / 22kHz (H : 22kHz) 4 H Select audio source for Scart 2 output (Switch K5) 5 H Select audio source for Scart 2 output (Switch K5) 6 H Audio deemphasis select (Switch K2) 7 H Audio deemphasis select (Switch K2) Reg 4 write only Bit (default BFHEX) 0 H Select source for video decoder O/P 1 H Select source for video decoder O/P 2 H Select source for video decoder O/P 3 H Stand-by or low power mode (H = low power) 4 H Select audio source for Scart 3 output (Switch K6) 5 H Select audio source for Scart 3 output (Switch K6) 6 L Black level adjust on Scart 3 video 7 H Black level adjust on Scart 3 video Reg 5 write only Bit (default B5HEX) 0 H FM deviation selection -- default value for 50kHz modulation 1 L FM deviation selection 2 H FM deviation selection 3 L FM deviation selection 4 H FM deviation selection 5 H FM deviation selection (L = double the FM deviation) 6 L Select 22kHz for I/O (Pin 29 / STV0056AF) 7 H Select TP50a (H) or I/O (Pin 29 / STV0056AF). TP50a for test only. Reg 6 write/read Bit (default 86HEX) 0 L Status of I/O 1 H Select data direction of I/O 1 ( H = output) 2 H Select frequency synthesizer 1 OFF/ON (L = OFF) 3 L Select frequency synthesizer 2 OFF/ON (L = OFF) 4 L Select RF source (L = OFF) to FM det 1 5 L Select RF source (L = OFF) to FM det 2 6 L Select frequency for PLL synthesizer - LSB (bit 0) of 10-bit value 7 H Select frequency for PLL synthesizer - bit 1 of 10-bit value
19/27
STV0056AF
CONTROL REGISTERS (continued) Reg 7 write/read Bit (default AFHEX) 0 H Select frequency for PLL synthesizer - bit 2 of 10-bit value 1 H Select frequency for PLL synthesizer 2 H Select frequency for PLL synthesizer 3 H Select frequency for PLL synthesizer 4 L Select frequency for PLL synthesizer 5 H Select frequency for PLL synthesizer 6 L Select frequency for PLL synthesizer 7 H Select frequency for PLL synthesizer - bit 9, MSB (10th bit) of 10-bit value Reg 8 Bit 0 1 2 3 4 5 6 7 read only Subcarrier detection (DET 1) (L = No subcarrier) Not used Read frequency of watchdog 1 - LSB (bit 0) of 10-bit value Read frequency of watchdog 1 - bit 1 of 10-bit value Subcarrier detection (DET 2) (L = No subcarrier) Not used Read frequency of watchdog 2 - bit 0 of 10-bit value Read frequency of watchdog 2 - bit 1 of 10-bit value
Reg 9 read only Bit (default AFHEX) 0 Read frequency of watchdog 1 - bit 2 of 10-bit value 1 Read frequency of watchdog 1 2 Read frequency of watchdog 1 3 Read frequency of watchdog 1 4 Read frequency of watchdog 1 5 Read frequency of watchdog 1 6 Read frequency of watchdog 1 7 Read frequency of watchdog 1 - bit 9, MSB (10th bit) of 10-bit Reg 0A read only Bit 0 Read frequency of watchdog 2 - bit 2 of 10-bit value 1 Read frequency of watchdog 2 2 Read frequency of watchdog 2 3 Read frequency of watchdog 2 4 Read frequency of watchdog 2 5 Read frequency of watchdog 2 6 Read frequency of watchdog 2 7 Read frequency of watchdog 2 - bit 9, MSB (10th bit) of 10-bit
20/27
STV0056AF
CONTROL REGISTERS (continued) Video Mux Truth Tables Register 2 <0:2> Scart 1 video output control Register 3 <0:2> Scart 2 video output control Register 4 <0:2> Scart 3 decoder output control The truth table for the three scart outputs are the same.
Register 2/3/4 Bit<2> 0 0 0 0 1 1 1 1 Bit<1> 0 0 1 1 0 0 1 1 Register 4 Bit <7> 0 1 0 1 Bit <6> 0 0 1 1 -150mV 0 (default) +150mV +300mV Bit<0> 0 1 0 1 0 1 0 1 Baseband video De-emphasized video Normal video Scart 3 return Scart 2 return Scart 1 return Nothing selected High Z or low power (default) Black Level Adjust on Scart 3 Video Output
Audio Mux Truth Tables
Register 2 Bit <5> 0 1 0 1 Bit <4> 0 0 1 1 Register 3 Bit <7> 0 1 0 1 Bit <6> 0 0 1 1 Register 0 Bit <6> 0 1 X X Bit <5> X X 0 1 Register 3 Bit <5> 0 1 0 1 Bit <4> 0 0 1 1 Register 4 Bit <5> 0 1 0 1 Bit <4> 0 0 1 1 A C B C A B A B A B ANRS I/O Select Noise reduction OFF Noise reduction ON (default) I/P = PLL I/P = Scart 3 return Switch K5/Audio Source Selection for Scart 2 Aux Audio Output PLL output Scart 3 return Audio deemphasis (K2 switch O/P) High Z or low power state (default) Switch K6/Audio Source Selection for Scart 3 Audio Decoder Output PLL output Audio deemphasis (K2 switch O/P) Scart 2 return High Z or low power state (default) A C B B Audio Deemphasis No deemphasis J17 50s 75s (default) Switch K3 & K4 A C B Switch K1/Audio Source Selection for Volume Output Volume Output Audio deemphasis (K2 switch O/P) Scart 2 return Scart 3 return High Z or low power (default) Switch K2/Audio Deemphasis
21/27
STV0056AF
CONTROL REGISTERS (continued)
Register 2 Bit <7> 0 1 1 Bit <6> 0 0 1 Left / Right / Stereo on Volume Output Mono left / channel 1 Mono right / channel 2 Stereo left & right (default)
Register 5 : FM Deviation Selection
4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected Nominal Carrier Modulation Bit 5 = 0 Do not use Do not use Do not use Cal. set. (2V) 592kHz 534kHz 484kHz 436kHz 396kHz 358kHz 322kHz 292kHz 266kHz 240kHz 218kHz 196kHz 179kHz 161kHz 146kHz 122kHz 120kHz 109kHz 98kHz 89kHz 78kHz 71kHz 65kHz 58kHz 53kHz 48.6kHz 43.8kHz 39.6kHz Bit 5 = 1 cal : do not use = 0.3373V offset on VCO cal : do not use = 0.3053V offset on VCO cal : do not use = 0.2763V offset on VCO calibration setting (1V offset on VCO) 296kHz modulation 267kHz modulation 242kHz 218kHz 198kHz 179kHz 161kHz 146kHz 133kHz 120kHz 109kHz 98.3kHz 89.7kHz 80.9kHz 73.1kHz 66.0kHz 60.0kHz 54.4kHz = default power up state 49.1kHz 44.3kHz 39.8kHz 35.9kHz 32.4kHz 29.1kHz 26.7kHz 24.3kHz 21.9kHz 19.7kHz
Example : Default power up state 54.4kHz 54.4kHz.
Register 1 Bit <7> 0 0 1 1
Register 3 Bit <3> 0 1 0 1 Deemphasis Deemphasis Deemphasis Deemphasis 1 (default) 1 + 22kHz 2 2
Video Deemphasis/22kHz
Register 5 Bit <7> 0 0 1 1 Bit <6> 0 1 0 1
Digital I/O (STV0056AF pin 29) I/O (refer to Register 6 Bit <0> Bit <1>) 22kHz Do not use (for test only) (default) 22kHz
22/27
STV0056AF
FM DEMODULATION SOFTWARE ROUTINE With the STV0056AFcircuit, for each channel,three steps are required to acheive a FM demodulation : - 1st step :To set the demodulation parameters : * FM deviation selection, * Subcarrier frequency selection. - 2nd step : To implement a waiting loop to check the actual VCO frequency. - 3rd step :To close the demodulationphase locked loop (PLL). Refering to the FM demodulation block diagram (page 12), the frequency synthesis block is common to both channels (left and right) ; consequently two completesequenceshave to be done one after the other when demodulating stereo pairs. Detailed Description Conventions : - R = Stands for Register - B = Stands for Bit
Example : R05 B2 = Register 05, Bit 2
For clarity, the explanations are based on the following e xa mp le : st ere o p air 7 .0 2MHz /L 7.20MHz/R, deviation 50kHz max.
1st STEP (LEFT) : SETTING THE DEMODULATION PARAMETERS
A. The FM deviation is selected by loading R5 with the appropriate value. (see R5 truth table). NB : Very wide deviations (up to 592kHz) can be accomodated when R5 B5 is low. Corresponding bandwidth can be calculated as follows : Bw 2 (FM deviation + audio bandwidth) Bw 2 (value given in table + audio bandwidth) In the example : R5Bits 7 6 5 4 3 2 1 0 X X 1 1 0 1 1 0 B. The subcarrier frequency is selected by launching a frequencysynthesis (the VCO is driven to the wanted frequency). This operation requires two actions : - To connect the VCO to the frequency synthesis loop. Refering to the FM block diagram (page 12): * SW4 closed R6 B2 = H * SW3 to bias R6 B4 = L * SW2 to bias R6 B3 = L * SW1 opened R6 B5 = L - To load R7 and R6 B6 B7 with the value corresponding to the left channel frequency. This 10 bits value is calculated as follows : Subcarrier frequency = coded value x 10kHz (10kHz is the minimum step of the frequency synthesis function) Considering that the tunning range is comprised between 5 to 10MHz, thecoded value is a number 10 between 500 and 1000 (2 = 1024) then 10 bits are required. Example : 7.02MHz = 702 x 10kHz 702 1010 1111 10 AF + 10 R7 is loaded with AF and R6 B6 : L, R6 B7 : H. The Table 1 gives the setting for the most common subcarrier frequencies.
Table 1 : Frequency Synthesis Register Setting for the Most Common Subcarrier Frequencies
Subcarrier Frequency (MHz) 5.58 5.76 5.8 5.94 6.2 6.3 6.4 6.48 6.5 6.6 6.65 6.8 6.85 7.02 7.20 7.25 7.38 7.56 7.74 7.85 7.92 8.2 8.65 Register 7 (Hex) 8B 90 91 94 9B 9D A0 A2 A2 A5 A6 AA AB AF B4 B5 B8 BD C1 C4 C6 CD D8 Register 6 Bit 7 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 Bit 6 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1
23/27
STV0056AF
FM DEMODULATION SOFTWARE ROUTINE (continued)
2nd STEP (LEFT) : VCO FREQUENCY CHECKING (VCO)
This second step is actually a waiting loop in which the actual running frequency of the VCO is measured. To exit of this loop is allowed when : Subcarrier Frequency - 10kHz Measured Frequency Subcarrier Frequency + 10kHz ( 10kHz is the maximum dispersion of the frequency synthesis function). In practice, R8 B2 B3 and R9 are read and compared to the value loaded in R6 B6 B7 and R7 1 bit. Note : The duration of this step depends on how large is frequency difference between the start frequency and the targeted frequency. Typically : - the rate of change of the VCO frequencyis about 3.75MHz/s (Cpump = 10F) - In addition to this settling time, 100ms must be added to take into account the sampling period of the watchdog.
In practice : - SW3 closed R6 B4 = H - SW4 opened R6 B2 = L After this sequence of 3 steps for left channel, a similar sequence is needed for the right channel.
Note : In the sequence for the right, there is no need to again select the FM deviation (once is enough for the pair). General Remark Before to enable the demodulated signal to the audio output, it is recommandedto keep the muting and to check whether a subcarrier is present at the wanted frequency. Such an informationis available in R8 B0 and R8 B4 which can be read.
Two different strategies can be adoptedwhen enabling the output : - Either both left and right demodulatedsignals are simultaneously authorized when both channel are ready. - Or while the right channelsequenceis running,the already ready left signal is sent to the left and right outputs and the real stereo sound L/R is output when bothchannelsare ready. This second option gives sound a few hundreds of ms before the first one.
3rd STEP (LEFT)
TheFM demodulationcan be startedby connecting the VCO to the phase locked loop (PLL).
24/27
STV0056AF
R54 3.3k R57 24k
TV SCART
R55 1.5k
C63 220nF C62 8.2nF
C61 1.5nF
C100 220nF
Q4 BC557 C115 220nF
R56 10k R117 24k
R100 75
1
2 3 5 7 9 11 13 15 17 19 21
4
6
8
10
12
14
16
18
20
J1
C64 1.5nF
C65 100nF
Q103 BC557
V CCA
R116 10k R58 43k R59 1.2M
C114 8.2nF
J6 VCCV L J5 V R3 470 R2 68
R
C3 2.2F
C2 2.2F
Q1 BC547
C66 100nF
C60 1.5nF
R114 3.3k R60 1.2M R53 43k
R115 1.5k
C113 1.5nF
J4
R50 47.5k 1%
8.2V
64
63 1
62
61
60
59
58
57
56
55
54
53
52
51
50
49 48 2 47 3 4 46 45 5 44
C50 10F 16V
TYPICAL APPLICATION (3 SCARTS, PAL/SECAM Europe Apllication)
VCR SCART
C4 220nF R6 75
+
R37 560k
C7 2.2F
C8 2.2F
1
2 3 5 7 9 11 13 15 17 19 21
4
6
8
10
12
14
16
18
20
J2
V CCA TDK FILTER SEL5618 C11 8.2nF
C45 100nF
C6 2.2F
C5 2.2F
R5 68
VCCV
1 2
3
6
R16 1k
R10 10k R11 1.5k R9 5.1k
43 7 8
+ C13 10F 16V C12 100pF
Q2 BC547 R4 470
42
STV0056AF
9 10
VCCV
41 40
C42
R15 1k
TQFP64
11
C43
39 38 12 13 37 36
100nF
100nF
R36
560k
DECODER SCART
C101 220nF R102 75
C103 2.2F
C104 2.2F
10F 16V
14
21
35
J3
1
2 3 5 7 9 11 13 15 17 19
4
6
8
10
12
14
16
18
20
VCCV
C26 10F 16V
R10368 J7 Q101 BC547 R101 470 TUNER INPUT
15 16
C25 100pF R17 470 C23 8.2nF
34 33 17
R48 75 R18 1k L4 47H
C24 27pF
C105 2.2F
C102 2.2F
18
19
20
21
22
C56 100nF
23
24
25
26
27
28
29
30
31
32
VDD C29 22pF 4MHz or 8MHz Crystal C108 8.2nF
+
C41
8.2V
R40 180k
C38 22pF
C47 22pF
R105 36k
R33 180k
J11 5V 1 GND 1 J12
L1 22H
+ C31 220F 16V
V DD C30 100nF
J13 12V 1 GND 1 J14
L2 22H
+ C33 220F 16V + C35 220F 16V
VCCV C32 100nF VCCA C34 100nF
R104 4.7k
R32 82k
C39 2.7nF
C46 2.7nF
R41 82k
+
C40 470F 16V
3 x 1N4148
R34 27k
R39 27k
5V SDA SCL GND
J10 1 2 3 4
R107 4.7k
R106 36k
3 x 1N4148
C65 47pF
C66 47pF
C107 8.2nF
C37 22pF
R113 560k
R51 560k
J8 I/O 1
C48 22pF
C112 100nF
C58 100nF
25/27
0056F-35.EPS
STV0056AF
TWIN TUNER APPLICATION Easy parallel connection of the outputs to the scarts without any additional switching hardware. This configuration is possible due to the high impedance mode that can be selected for each audio and video outputs.
Video TUNER 1
28
I2C Bus
S T V 0 0 5 6 A F
64 2 63
TV SCART 62-3 5-7 23-24 Audio 2 Video
VCR SCART Audio 2 Video TUNER 2
5V
28
23-24
26/27
0056F-36.EPS
S T V 0 0 5 6 A F
64 2 63
DECODER SCART 62-3 5-7 Audio 2
STV0056AF
PACKAGE MECHANICAL DATA 64 PINS - PLASTIC QUAD FLAT PACK (THIN) (TQFP)
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C L1
E
L
B
K
TF6 Q4 P
Dimensions A A1 A2 B C D D1 D3 e E E1 E3 K L L1
Min. 0.05 1.35 0.18 0.12
Millimeters Typ.
1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00
Max. 1.60 0.15 1.45 0.28 0.20
Min. 0.002 0.053 0.007 0.0047
Inches Typ.
1 0o (Min.), 7o (Max.) 0.75 0.0157
0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393
Max. 0.063 0.006 0.057 0.011 0.0079
0.40
0.0295
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
27/27
TQFP64.TBL
PMTQFP64.EPS

▲Up To Search▲

Price & Availability of STV0056AF

	To Download STV0056AF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .